-- huanor_reset Controller v1.0
-- 2012.01.08
-- http://www.huanor.com/

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY RST IS
GENERIC (
	MS	: integer := 500;	-- delay x ms;
	NS	: integer := 50		-- ns cnt
);
PORT
(
	clk		: in std_logic ;
	nrsti	: in std_logic ;
	nrsto	: out std_logic
);
END RST;

ARCHITECTURE ARC OF RST IS

constant rst_on		: std_logic := '0';
constant rst_off	: std_logic := '1';
constant act_on		: std_logic := '1';
constant act_off	: std_logic := '0';

signal nrsto_buf	: std_logic;

signal ms_cnt	: natural range 0 to MS-1;
signal us_cnt	: natural range 0 to 999;
signal ns_cnt	: natural range 0 to NS-1;

BEGIN

nrsto <= nrsto_buf;

process(nrsti, clk)
begin
if(nrsti=rst_on) then
	nrsto_buf <= rst_on;
	ms_cnt <= 0;
	us_cnt <= 0;
	ns_cnt <= 0;
elsif( rising_edge(clk) ) then	
	if ns_cnt>=ns_cnt'high then	-- 1ns ++
		ns_cnt <= 0;				
		if us_cnt>=us_cnt'high then	-- 1us ++
			us_cnt <= 0;			
			if ms_cnt>=ms_cnt'high then	-- 1ms ++
				ms_cnt <= ms_cnt'high;				
			else
				ms_cnt <= ms_cnt + 1;
			end if;
		else
			us_cnt <= us_cnt + 1;
		end if;
	else
		ns_cnt <= ns_cnt + 1;
	end if;	
	if ms_cnt>=ms_cnt'high then	-- stop end
		nrsto_buf <= rst_off;			
	else
		nrsto_buf <= rst_on;
	end if;
end if;
end process;

END ARC;